1. Field of the Invention
The present invention relates generally to memory module sockets used to interconnect memory modules with other computer components. More specifically, the present invention relates to a memory module socket which has a reversed pinout configuration and which is particularly suitable for memory device testing.
2. State of the Art
Semiconductor integrated circuit devices are manufactured on wafers or other substrates of semiconductor material. Conventionally, many devices are manufactured on a single wafer and individual devices or groups of devices are singulated, or cut, from the wafer and packaged. The devices are tested at various points during the manufacturing process, e.g., while they are still in the wafer form, in die form (after singulation but prior to packaging), and after packaging.
Testing may be directed towards detection of flaws or errors regarding one or more facets of semiconductor fabrication. For example, one stage of testing concerns the physical structure of the device. Such testing may include the use of various techniques known in the art such as emission microscopes or X-ray analysis. Testing of the structure typically focuses on whether discernible errors or flaws develop during the physical formation of the semiconductor die. Such flaws may be the result of one or more processing steps improperly performed, such as, for example, over-etching. Flaws are also developed as a result of contaminants introduced during the fabrication process. Indeed, numerous factors exist which may influence the introduction and development of such flaws or errors.
Another facet of testing concerns the functionality and performance of the device. This typically involves connecting the device to a circuit such that a signal or combination of signals may be passed through the device. The response by the device to the signal is then monitored, with the output value being compared to values expected to be obtained from a properly functioning device. Tests may involve a particular signal or combination of signals being delivered repetitively, perhaps under extreme environmental or operational conditions (temperature, voltage, etc.) outside of normal parameters in order to identify a device which would fail after a shorter than usual period of use. Other tests may involve a number of different signals or signal combinations delivered in sequence. One method for testing a memory device is to deliver the same signal or signal combination to multiple identical subsections of the device simultaneously and compare the values read from the subsections (xe2x80x9ccompression testingxe2x80x9d). If all of the respective read values match, the test has been passed, while a mismatch between respective values read from any of the subsections indicates a device malfunction and failure of the test.
Another stage of testing may concern the compatibility of the semiconductor device with other components. For example, it becomes desirable to confirm the compatibility of a memory device having a specific design with the multitude of personal computer motherboards currently available on the market. Such testing would involve connecting identical memory modules to motherboards of different design and manufacturing origin and then subjecting the memory modules to an otherwise identical testing process. This type of testing helps to assure computer manufacturers as well as consumers that the device will function as expected regardless of who may be the manufacturer of other interconnected components.
The ultimate objective of testing is to produce a device having verified reliability and quality. While this objective is of extreme importance, the efficiency with which testing is performed is also an important concern. It becomes desirable to reduce testing time whenever possible without compromising the integrity of the testing process. A reduction in test time, without a sacrifice in quality, results in greater manufacturing throughput and thus lowers manufacturing costs. Reduced manufacturing costs are very desirable in that they ultimately lead to higher profits for the company, as well as a savings to the consumer.
One method of reducing testing time without compromising the integrity of the testing process is to perform batch tests. In other words, numerous devices are tested coterminously instead of testing each device sequentially, one at a time. An example of such testing, with regards to memory devices, can be better understood with reference to FIG. 1. A testing apparatus 10 may include a plurality of motherboards 12 housed in a holding device such as a cabinet or a frame 14. A plurality of memory devices, such as dynamic random access memory (DRAM) or other memory modules 16, are appropriately coupled to individual memory sockets 18. Each memory socket 18 is operatively coupled to a motherboard 12 with each motherboard 12 including multiple memory sockets 18. Thus, each motherboard 12 is capable of accommodating several memory modules 16 during a given testing operation.
It is noted the testing apparatus 10 is illustrated as holding identical motherboards. However, as noted above, such a testing apparatus 10 may accommodate various motherboard styles, designs, and sizes. Thus, the system as described may be employed in various facets of testing, including compatibility testing.
With the memory modules 16 in place, functional testing or, alternatively, compatibility testing of the memory modules 16 is conducted. As described above, the motherboards 12 provide a signal, or signals, to the memory modules 16 and then monitor the responsive output of each memory module 16. The configuration as described above allows numerous memory modules 16 to be tested in a relatively short amount of time. However, while the above described system allows for a greater quantity of devices to be tested at a given time, the turnaround time in removing tested modules and subsequent installation of untested modules is less than optimal.
One problem with a testing apparatus configuration such as is illustrated in FIG. 1 is that, in an effort to maximize the number of memory modules 16 being tested at a given time, the ability to remove and replace the memory modules 16 becomes compromised. This essentially results from the density and close proximity of the motherboards 12 within the cabinet or frame 14 combined with the configuration and orientation of the memory sockets 18 on the motherboard 12. A typical motherboard 12 is configured such that the memory sockets 18 are mounted along a planar surface of the motherboard 12 so that memory modules 16 respectively inserted therein extend transversely away from the motherboard 12. Furthermore, the memory sockets 18 are typically fixed in their locations by mechanical means including soldering, riveting and other techniques known in the art. Therefore, to extract a memory module 16 from a memory socket 18, it must be withdrawn from memory socket 18 in a direction perpendicular to the planar surface of the motherboard 12. However, in a testing apparatus 10 where the motherboards 12 are configured in close vertical proximity to each other, removal of the memory module 16 becomes rather difficult and time consuming.
For example, still referring to FIG. 1, distance xe2x80x9cAxe2x80x9d represents the distance between the top of a memory module 16 and an adjacent motherboard 12. Distance xe2x80x9cBxe2x80x9d, on the other hand, represents the minimum distance that the memory module 16 must travel through to be removed from the memory socket 18 (i.e., the distance required for the bottom of the memory module 16 to clear the top of the memory socket 18). It may often be the case that distance xe2x80x9cBxe2x80x9d is greater than distance xe2x80x9cAxe2x80x9d. In such a case it becomes physically impossible to remove the memory modules 16 (or insert them) unless the motherboards 12 are first removed from the frame 14. In the instance of a cabinet or frame holding a plurality of motherboards 12, each having a plurality of memory sockets 18, replacement of the memory modules 16 thus becomes a laborious and time consuming task. Even if the motherboards 12 are spaced in cabinet or frame 14 so that distance xe2x80x9cAxe2x80x9d becomes larger than distance xe2x80x9cBxe2x80x9d, it remains difficult for an individual to maneuver his or her hands in between the vertically superimposed motherboards 12 and complete the task of insertion or removal of the memory modules 16 with any degree of efficiency.
It is conceivable that the motherboards 12 might be arranged such that the upper planar surface of each motherboard 12 is adjacent to and runs parallel with the vertical member of the cabinet or frame 14. However, this is not an ideal solution either. While this would allow the memory modules 16 to be exposed to the space external to the cabinet or frame 14 and be removed from memory sockets 18 in a horizontal direction, an access problem may still exist. For example, expansion slots 20, while shown empty in FIG. 1, typically accommodate peripheral cards allowing communication from the motherboard 12 to additional devices. When peripheral cards are installed, they present additional difficulties regarding access to the memory modules 16 due to their close proximity to the memory modules 16 on the same top surface of the motherboard 12. Similarly, other semiconductor components and device connections may create access difficulties based on the dense arrangement of all these components on the same surface of the motherboard 12.
In view of the above-enumerated shortcomings in the state of the art, it would be advantageous to reduce the amount of time required for the removal and replacement of memory modules from a testing apparatus.
It would also be advantageous to provide enhanced access to specific semiconductor components during functional testing or compatibility testing.
It would also be advantageous to provide an apparatus or system which could be configured for use with an automatic handling unit to remove and replace memory modules in a testing apparatus. Such an apparatus or system should be flexible and adaptable to a user""s needs, as well as simple to fabricate and operate.
One exemplary embodiment of the present invention comprises a memory socket for facilitating a test connection of a memory module with a motherboard. The memory socket includes an insulative housing having an elongated channel-shaped socket formed within the housing. The elongated socket is configured to have a memory module such as, for example, a single in-line memory module (SIMM) or dual in-line memory module (DMM), coupled thereto. A set of conductive contacts is arranged within the elongated socket for proper electrical connection with respective, cooperative pinout contacts of the memory module. A second set of conductive contacts, electrically connected to the first set of conductive contacts and configured for connection to the motherboard, is arranged in a reverse or mirror image arrangement of a conventional memory socket second conductive contact pattern.
The first surface of the motherboard is defined to have at least the central processing unit (CPU) or xe2x80x9cprocessorxe2x80x9d (or corresponding processor socket) mounted to it, while the second, opposing surface is where the inventive memory socket is to be mounted. The second, reversed set of conductive elements may comprise conductive pins which will pass from the memory socket adjacent the second surface through corresponding apertures in the motherboard sized and arranged to receive conductive pins of a conventional memory socket mounted to the first surface. The pins of the inventive memory socket may, by way of example only, be arranged in at least two parallel rows forming an asymmetrical pin set such that the same socket would not mate with the apertures of the motherboard on both the first surface and the second surface.
Another exemplary embodiment of the present invention comprises a motherboard. The motherboard includes a dielectric substrate having a first surface and a second, opposing surface and bears a plurality of conductive traces. A processor, or a processor socket configured to couple to a processor, is mounted at a processor location on the first surface of the motherboard. A memory socket is mounted on the second surface of the motherboard and is electrically coupled to the processor location by way of conductive traces of the motherboard. A plurality of memory sockets may be mounted to the second surface as described if the motherboard is configured with traces for multiple memory sockets. The motherboard may also include additional devices such as one or more expansion slots, or other semiconductor devices, coupled to the first surface of the motherboard and electrically coupled to the processor via traces.
The memory socket may be configured to receive one of various types of memory modules known in the art. The various types of memory modules may include, for example, 30 pin SIMM modules, 72 pin SIMM modules, 168 pin DIMM modules, the various forms of small outline DIMM modules typically used in notebook type computers, or RMM modules incorporating the so-called Rambus memory dice.
In accordance with yet another exemplary embodiment of the invention, a system for testing memory modules is provided. The test system includes a plurality of motherboard assemblies which may be mounted to a frame. Each motherboard assembly includes a dielectric substrate having first and second opposing surfaces and bears a series of circuit traces. A processor, or a processor socket adapted to receive a processor at a processor location, is mounted on the first surface of each motherboard. At least one memory socket is mounted on the second surface of each motherboard assembly and is electrically coupled to the processor or socket by way of traces. Each motherboard is coupled to an input device for providing electrical test signals and a monitoring device for receiving output signals from the motherboard assembly. The system may be configured for use with an automated handling unit for inserting memory modules in the memory sockets and removing and replacing those memory modules after a testing cycle has been completed.
In accordance with yet another exemplary embodiment of the invention, a method is provided for reconfiguring a motherboard for use in the testing of a memory device. In accordance with the method, a motherboard is provided having a dielectric substrate having first and second opposing surfaces and bearing a series of circuit traces defining a printed circuit. The motherboard further includes a processor, or processor socket, mounted to the first surface at a processor location and at least one conventional memory socket mounted to the first surface, wherein the processor and memory socket are electrically connected by means of traces. The conventional memory socket is removed from the first surface, and a memory socket according to the invention is mounted on the second surface and coupled to the processor through the same traces as the conventional memory socket. The reconfiguring process may include reflowing solder connections of the original, conventional memory socket to detach it from the first surface. The method may further include arranging an array of electrical contacts of the inventive memory socket in reverse or mirror image of the pattern of contacts so that they mate with the existing pattern of conductive elements on the motherboard arranged for coupling to conductive contacts of the conventional memory socket when the inventive memory socket is mounted to the second surface.